(Publisher of Peer Reviewed Open Access Journals)

International Journal of Advanced Technology and Engineering Exploration (IJATEE)

ISSN (Print):2394-5443    ISSN (Online):2394-7454
Volume-10 Issue-107 October-2023
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Paper Title : Error efficient LOB-based approximate multipliers for error-tolerant applications
Author Name : E. Jagadeeswara Rao and P. Samundiswary
Abstract :

Approximate computing (AC) was positioned at the forefront of research in the field of error-tolerant applications. One key facet of AC was the use of approximate arithmetic functions, which offered significant reductions in delay, area, and power consumption at the expense of accuracy. Among these arithmetic functions, multiplication was extensively employed and played a pivotal role in error-tolerance applications. However, as the bit width increased, the design metrics and accuracy of existing multiplication designs tended to reduce. In this paper, novel architectures for leading one-bit-based approximate multipliers (LOBAMs) were proposed, aimed at improving both accuracy and design metrics. This paper focused on 8 × 8 and 16 × 16 approximate multipliers (AMs) designed in 90 nm complementary metal oxide semiconductor technology. The simulation results confirmed that LOBAMs outperformed existing AMs, reducing mean relative error distance, mean error distance, worst-case of error, normalized error distance, and error distance by an average of 74.59%, 80.75%, 41.06%, 84.19%, and 72.3%, respectively. Furthermore, when the proposed LOBAMs were embedded into an image smoothing filter, they demonstrated superior performance in terms of peak signal-to-noise ratio and structural similarity index metric compared to prior AMs. Finally, the proposed LOBAMs were exhibited remarkable advancements in both accuracy and design metrics when compared to existing AMs. This work underscored the potential of LOBAMs to revolutionize AC and contribute to more efficient and accurate error-tolerant systems.

Keywords : Approximate computing, Error metrics, Quality metrics, Design metrics, LOB-based approach.
Cite this article : Rao EJ, Samundiswary P. Error efficient LOB-based approximate multipliers for error-tolerant applications. International Journal of Advanced Technology and Engineering Exploration. 2023; 10(107):1279-1292. DOI:10.19101/IJATEE.2023.10101561.
References :
[1]Mittal S. A survey of techniques for approximate computing. ACM Computing Surveys. 2016; 48(4):1-33.
[Crossref] [Google Scholar]
[2]Gupta V, Mohapatra D, Raghunathan A, Roy K. Low-power digital signal processing using approximate adders. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2012; 32(1):124-37.
[Crossref] [Google Scholar]
[3]Yang Z, Jain A, Liang J, Han J, Lombardi F. Approximate XOR/XNOR-based adders for inexact computing. In 13th international conference on nanotechnology 2013 (pp. 690-3). IEEE.
[Crossref] [Google Scholar]
[4]Han J, Orshansky M. Approximate computing: an emerging paradigm for energy-efficient design. In 18th European test symposium 2013 (pp. 1-6). IEEE.
[Crossref] [Google Scholar]
[5]Venkataramani S, Chakradhar ST, Roy K, Raghunathan A. Approximate computing and the quest for computing efficiency. In proceedings of the 52nd annual design automation conference 2015 (pp. 1-6).
[Crossref] [Google Scholar]
[6]Reddy KM, Vasantha MH, Kumar YN, Dwivedi D. Design and analysis of multiplier using approximate 4-2 compressor. AEU-International Journal of Electronics and Communications. 2019; 107:89-97.
[Crossref] [Google Scholar]
[7]Narayanamoorthy S, Moghaddam HA, Liu Z, Park T, Kim NS. Energy-efficient approximate multiplication for digital signal processing and classification applications. IEEE Transactions on Very Large Scale Integration Systems. 2014; 23(6):1180-4.
[Crossref] [Google Scholar]
[8]Di MG, Saggese G, Strollo AG, De CD, Petra N. Approximate floating-point multiplier based on static segmentation. Electronics. 2022; 11(19):1-23.
[Crossref] [Google Scholar]
[9]Strollo AG, Napoli E, De CD, Petra N, Saggese G, Di MG. Approximate multipliers using static segmentation: error analysis and improvements. IEEE Transactions on Circuits and Systems I: Regular Papers. 2022; 69(6):2449-62.
[Crossref] [Google Scholar]
[10]Ko HJ, Hsiao SF. Design and application of faithfully rounded and truncated multipliers with combined deletion, reduction, truncation, and rounding. IEEE Transactions on Circuits and Systems II: Express Briefs. 2011; 58(5):304-8.
[Crossref] [Google Scholar]
[11]Vahdat S, Kamal M, Afzali-kusha A, Pedram M. LETAM: a low energy truncation-based approximate multiplier. Computers & Electrical Engineering. 2017; 63:1-7.
[Crossref] [Google Scholar]
[12]Vahdat S, Kamal M, Afzali-kusha A, Pedram M. TOSAM: an energy-efficient truncation-and rounding-based scalable approximate multiplier. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2019; 27(5):1161-73.
[Crossref] [Google Scholar]
[13]Du Y, Chen Z, Cheng B, Shan W. Design and analysis of leading one/zero detector based approximate multipliers. Microelectronics Journal. 2023; 136:105783.
[Crossref] [Google Scholar]
[14]Lingamneni A, Basu A, Enz C, Palem KV, Piguet C. Improving energy gains of inexact DSP hardware through reciprocative error compensation. In proceedings of the 50th annual design automation conference 2013 (pp. 1-8).
[Crossref] [Google Scholar]
[15]Hashemi S, Bahar RI, Reda S. DRUM: a dynamic range unbiased multiplier for approximate applications. In IEEE/ACM international conference on computer-aided design 2015 (pp. 418-25). IEEE.
[Crossref] [Google Scholar]
[16]Zendegani R, Kamal M, Bahadori M, Afzali-kusha A, Pedram M. RoBA multiplier: a rounding-based approximate multiplier for high-speed yet energy-efficient digital signal processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2016; 25(2):393-401.
[Crossref] [Google Scholar]
[17]Garg B, Patel S. Reconfigurable rounding based approximate multiplier for energy efficient multimedia applications. Wireless Personal Communications. 2021; 118:919-31.
[Crossref] [Google Scholar]
[18]Rao EJ, Samundiswary P. Error-efficient approximate multiplier design using rounding based approach for image smoothing application. Journal of Electronic Testing. 2021; 37:623-31.
[Crossref] [Google Scholar]
[19]Rao EJ, Rao KT, Ramya KS, Ajaykumar D, Trinadh R. Efficient design of rounding-based approximate multiplier using modified Karatsuba algorithm. Journal of Electronic Testing. 2022; 38(5):567-74.
[Crossref] [Google Scholar]
[20]Gorantla A, P D. Design of approximate compressors for multiplication. ACM Journal on Emerging Technologies in Computing Systems. 2017; 13(3):1-7.
[Crossref] [Google Scholar]
[21]Angizi S, Jiang H, Demara RF, Han J, Fan D. Majority-based spin-CMOS primitives for approximate computing. IEEE Transactions on Nanotechnology. 2018; 17(4):795-806.
[Crossref] [Google Scholar]
[22]Moaiyeri MH, Sabetzadeh F, Angizi S. An efficient majority-based compressor for approximate computing in the nano ERA. Microsystem Technologies. 2018; 24:1589-601.
[Crossref] [Google Scholar]
[23]Shirinabadi FS, Reshadinezhad MR. A new twelve-transistor approximate 4: 2 compressor in CNTFET technology. International Journal of Electronics. 2019; 106(5):691-706.
[Crossref] [Google Scholar]
[24]Liu W, Zhang T, Mclarnon E, O’neill M, Montuschi P, Lombardi F. Design and analysis of majority logic-based approximate adders and multipliers. IEEE Transactions on Emerging Topics in Computing. 2019; 9(3):1609-24.
[Crossref] [Google Scholar]
[25]Anusha G, Deepa P. Design of approximate adders and multipliers for error tolerant image processing. Microprocessors and Microsystems. 2020; 72:102940.
[Crossref] [Google Scholar]
[26]Zhu Y, Liu W, Yin P, Cao T, Han J, Lombardi F. Design, evaluation and application of approximate‐truncated booth multipliers. IET Circuits, Devices & Systems. 2020; 14(8):1305-17.
[Crossref] [Google Scholar]
[27]Strollo AG, Napoli E, De CD, Petra N, Di MG. Comparison and extension of approximate 4-2 compressors for low-power approximate multipliers. IEEE Transactions on Circuits and Systems I: Regular Papers. 2020; 67(9):3021-34.
[Crossref] [Google Scholar]
[28]Yang Z, Li X, Yang J. Power efficient and high-accuracy approximate multiplier with error correction. Journal of Circuits, Systems and Computers. 2020; 29(15):2050241.
[Crossref] [Google Scholar]
[29]Khaleqi QJM, Ahmadinejad M, Moaiyeri MH. Ultraefficient imprecise multipliers based on innovative 4: 2 approximate compressors. International Journal of Circuit Theory and Applications. 2021; 49(1):169-84.
[Crossref] [Google Scholar]
[30]Sudharani B, Sreenivasulu G. Design of high speed approximate multipliers with inexact compressor adder. International Journal of Advanced Technology and Engineering Exploration. 2021; 8(80):887-902.
[Crossref] [Google Scholar]
[31]Fang B, Liang H, Xu D, Yi M, Sheng Y, Jiang C, et al. Approximate multipliers based on a novel unbiased approximate 4-2 compressor. Integration. 2021; 81:17-24.
[Crossref] [Google Scholar]
[32]Chandaka S, Narayanam B. Hardware efficient approximate multiplier architecture for image processing applications. Journal of Electronic Testing. 2022; 38(2):217-30.
[Crossref] [Google Scholar]
[33]Kumar UA, Bharadwaj SV, Pattaje AB, Nambi S, Ahmed SE. CAAM: compressor based adaptive approximate multiplier for neural network applications. IEEE Embedded Systems Letters. 2022; 15(3):117-20.
[Crossref] [Google Scholar]
[34]Ejtahed SA, Timarchi S. Efficient approximate multiplier based on a new 1-gate approximate compressor. Circuits, Systems, and Signal Processing. 2022:1-20.
[Crossref] [Google Scholar]
[35]Minaeifar A, Abiri E, Hassanli K, Darabi A. A high-accuracy low-power approximate multipliers with new error compensation technique for DSP applications. Circuits, Systems, and Signal Processing. 2023:1-9.
[Crossref] [Google Scholar]
[36]Sayadi L, Timarchi S, Sheikh-akbari A. Two efficient approximate unsigned multipliers by developing new configuration for approximate 4: 2 compressors. IEEE Transactions on Circuits and Systems I: Regular Papers. 2023; 70(4):1649-59.
[Crossref] [Google Scholar]
[37]Rahmani M, Babaeinik M, Ghods V, Khalesi H. Designing of an 8× 8 multiplier with new inexact 4: 2 compressors for image processing applications. Circuits, Systems, and Signal Processing. 2023:1-31.
[Crossref] [Google Scholar]
[38]Esmaeili E, Pesaran F, Shiri N. A high‐efficient imprecise discrete cosine transform block based on a novel full adder and wallace multiplier for bioimages compression. International Journal of Circuit Theory and Applications. 2023; 51(6):2942-65.
[Crossref] [Google Scholar]
[39]Yongxia S, Huaguo L, Bao F, Cuiyun J, Zhengfeng H, Maoxiang Y, et al. Design of approximate booth multipliers based on error compensation. Integration. 2023; 90:183-9.
[Crossref] [Google Scholar]
[40]Perri S, Spagnolo F, Frustaci F, Corsonello P. Designing energy-efficient approximate multipliers. Journal of Low Power Electronics and Applications. 2022; 12(4):1-17.
[Crossref] [Google Scholar]
[41]Deepsita SS, Kumar DM, Mahammad NS. Energy efficient error resilient multiplier using low-power compressors. ACM Transactions on Design Automation of Electronic Systems. 2022; 27(3): 1-26.
[Google Scholar]
[42]Zacharelos E, Nunziata I, Saggese G, Strollo AG, Napoli E. Approximate recursive multipliers using low power building blocks. IEEE Transactions on Emerging Topics in Computing. 2022; 10(3):1315-30.
[Crossref] [Google Scholar]
[43]Waris H, Wang C, Xu C, Liu W. AxRMs: approximate recursive multipliers using high-performance building blocks. IEEE Transactions on Emerging Topics in Computing. 2021; 10(2):1229-35.
[Crossref] [Google Scholar]
[44]Sk NM. Low power, high speed approximate multiplier for error resilient applications. Integration. 2022; 84:37-46.
[Crossref] [Google Scholar]
[45]Karthikeyan T, Sk NM. Energy efficient multiply-accumulate unit using novel recursive multiplication for error-tolerant applications. Integration. 2023; 92:24-34.
[Crossref] [Google Scholar]
[46]Liang J, Han J, Lombardi F. New metrics for the reliability of approximate and probabilistic adders. IEEE Transactions on Computers. 2012; 62(9):1760-71.
[Crossref] [Google Scholar]
[47]Kavand N, Darjani A, Rai S, Kumar A. Design of energy-efficient RFET-based exact and approximate 4: 2 compressors and multipliers. IEEE Transactions on Circuits and Systems II: Express Briefs. 2023; 70(9): 3644-8.
[Crossref] [Google Scholar]
[48]Garg B, Sharma GK. A quality-aware energy-scalable gaussian smoothing filter for image processing applications. Microprocessors and Microsystems. 2016; 45:1-9.
[Crossref] [Google Scholar]
[49]Wang Z, Bovik AC, Sheikh HR, Simoncelli EP. Image quality assessment: from error visibility to structural similarity. IEEE Transactions on Image Processing. 2004; 13(4):600-12.
[Crossref] [Google Scholar]
[50]Kumar RK, Joe DA. Behavioral level simulation of vedic multiplier for ALU. Journal of Advanced Research in Dynamical and Control Systems. 2017; 9(16):1231-49.
[Google Scholar]
[51]Han T, Carlson DA. Fast area-efficient VLSI adders. In IEEE 8th symposium on computer arithmetic 1987 (pp. 49-56). IEEE.
[Crossref] [Google Scholar]