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International Journal of Advanced Computer Research (IJACR)

ISSN (Print):2249-7277    ISSN (Online):2277-7970
Volume-4 Issue-14 March-2014
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Paper Title : FPGA Implementation of High Throughput Digital QPSK Modulator using Verilog HDL
Author Name : K.Anitha,Umesharaddy, B.K.Sujatha
Abstract :

This paper proposes a Quadrature Phase Shift Keying (QPSK) using two different methods. QPSK is one of the forms of Phase Shift Keying (PSK) modulation scheme. Generally a conventional QPSK modulator with Direct Digital Synthesizer (DDS) and arithmetic multiplier separates base band signal into I and Q phase which consumes low throughput with complexity in hardware implementation. Hence to generate high throughput QPSK modulator, the first proposal usesan up and down accumulator for carrier generator instead of DDS and arithmetic multiplier is modified as BOOTH multiplier. The second proposed method will produce the QPSK signal which is based on stored QPSK phase data in ROM which eliminates completely the DDS and multiplier blocks of the modulator.

Keywords : QPSK Modulation, Booth Algorithm, Verilog, FPGA.
Cite this article : K.Anitha,Umesharaddy, B.K.Sujatha, " FPGA Implementation of High Throughput Digital QPSK Modulator using Verilog HDL " , International Journal of Advanced Computer Research (IJACR), Volume-4, Issue-14, March-2014 ,pp.217-222.