(Publisher of Peer Reviewed Open Access Journals)

International Journal of Advanced Computer Research (IJACR)

ISSN (Print):2249-7277    ISSN (Online):2277-7970
Volume-3 Issue-12 September-2013
Full-Text PDF
Paper Title : Implementation of MAC by using Modified Vedic Multiplier
Author Name : Sreelekshmi M. S., Farsana F. J., Jithin Krishnan, Rajaram S, Aneesh R
Abstract :

Multiplier Accumulator Unit (MAC) is a part of Digital Signal Processors. The speed of MAC depends on the speed of multiplier. So by using an efficient Vedic multiplier which excels in terms of speed, power and area, the performance of MAC can be increased. For this fast method of multiplication based on ancient Indian Vedic mathematics is proposed in this paper. Among various method of multiplication in Vedic mathematics, Urdhva Tiryagbhyam is used and the multiplication is for 32 X 32 bits. Urdhva Tiryagbhyam is a general multiplication formula applicable to all cases of multiplication. Adder used is Carry Look Ahead adder. The proposed design shows improvement over carry save adder.

Keywords : MAC, Vedic multiplier, VHDL, Carry Look Ahead adder.
Cite this article : Sreelekshmi M. S., Farsana F. J., Jithin Krishnan, Rajaram S, Aneesh R, " Implementation of MAC by using Modified Vedic Multiplier " , International Journal of Advanced Computer Research (IJACR), Volume-3, Issue-12, September-2013 ,pp.11-15.