Abstract

A novel circuit topology for performing addition and subtraction operations, suitable for low-voltage, low-power, and high-speed digital very large scale integration (VLSI) circuits, is proposed in this paper. The proposed adder/subtractor leverages the multi-input capability of floating-gate metal oxide semiconductor (FGMOS) transistors to reduce the number of components required for executing both operations within a single circuit, thereby minimizing chip area. This circuit is well-suited for the design of low-voltage, low-power, high-speed arithmetic logic units (ALUs) intended for fast computing applications. The proposed design occupies a chip area of 132.44 µm², dissipates 37 µW of power, and achieves a delay of 0.045 ns, resulting in a power-delay product of 1.67 × 10⁻¹⁵ J. Furthermore, the circuit has been extended to implement 2-bit, 4-bit, and n-bit parallel adder/subtractor configurations. Its performance has been validated through simulation program with integrated circuit emphasis (PSpice) simulations conducted using 0.13 µm complementary metal oxide semiconductor (CMOS) technology with level 7 parameters at a supply voltage of 1 V.

Keywords

Floating-gate MOS transistor, Adder-subtractor circuit, Low-power VLSI design, High-speed arithmetic logic unit (ALU), CMOS, Power delay product.

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