International Journal of Advanced Technology and Engineering Exploration ISSN (Print): 2394-5443    ISSN (Online): 2394-7454 Volume-12 Issue-128 July-2025
  1. 4774
    Citations
  2. 2.8
    CiteScore
Application of multiple-input floating-gate MOS transistor for implementing a full adder/subtractor in high-speed ALUs

Mohd Javed1, Susheel Sharma1 and Rockey Gupta1

Department of Electronics,University of Jammu, Jammu, Jammu and Kashmir,India1
Corresponding Author : Susheel Sharma

Recieved : 07-May-2024; Revised : 26-June-2025; Accepted : 28-June-2025

Abstract

A novel circuit topology for performing addition and subtraction operations, suitable for low-voltage, low-power, and high-speed digital very large scale integration (VLSI) circuits, is proposed in this paper. The proposed adder/subtractor leverages the multi-input capability of floating-gate metal oxide semiconductor (FGMOS) transistors to reduce the number of components required for executing both operations within a single circuit, thereby minimizing chip area. This circuit is well-suited for the design of low-voltage, low-power, high-speed arithmetic logic units (ALUs) intended for fast computing applications. The proposed design occupies a chip area of 132.44 µm², dissipates 37 µW of power, and achieves a delay of 0.045 ns, resulting in a power-delay product of 1.67 × 10⁻¹⁵ J. Furthermore, the circuit has been extended to implement 2-bit, 4-bit, and n-bit parallel adder/subtractor configurations. Its performance has been validated through simulation program with integrated circuit emphasis (PSpice) simulations conducted using 0.13 µm complementary metal oxide semiconductor (CMOS) technology with level 7 parameters at a supply voltage of 1 V.

Keywords

Floating-gate MOS transistor, Adder-subtractor circuit, Low-power VLSI design, High-speed arithmetic logic unit (ALU), CMOS, Power delay product.

Cite this article

Javed M, Sharma S, Gupta R. Application of multiple-input floating-gate MOS transistor for implementing a full adder/subtractor in high-speed ALUs. International Journal of Advanced Technology and Engineering Exploration. 2025;12(128):1143-1161. DOI : 10.19101/IJATEE.2024.111100725

References
[1]
Foroutan V, Taheri M, Navi K, Mazreah AA. Design of two low-power full adder cells using GDI structure and hybrid CMOS logic style. Integration. 2014; 47(1):48-61.
[Crossref] [Google Scholar]
[2]
Uma R, Dhavachelvan P. Modified gate diffusion input technique: a new technique for enhancing performance in full adder circuits. Procedia Technology. 2012; 6:74-81.
[Crossref] [Google Scholar]
[3]
Tung CK, Shieh SH, Cheng CH. Low‐power high‐speed full adder for portable electronic applications. Electronics Letters. 2013; 49(17):1063-4.
[Crossref] [Google Scholar]
[4]
Dhar K, Chatterjee A, Chatterjee S. Design of an energy efficient, high speed, low power full subtractor using GDI technique. In proceedings of the students' technology symposium 2014 (pp. 199-204). IEEE.
[Crossref] [Google Scholar]
[5]
Sharma U, Jhamb M. A novel and voltage resilient design of ultra-high-speed low power keeper based full adder. Circuits, Systems, and Signal Processing. 2024; 43(12):7951-71.
[Crossref] [Google Scholar]
[6]
Mahendran G. CMOS full adder cells based on modified full swing restored complementary pass transistor logic for energy efficient high speed arithmetic applications. Integration. 2024; 95:102132.
[Crossref] [Google Scholar]
[7]
Rodriguez-villegas E. Low power and low voltage circuit design with the FGMOS transistor. Stevenage: Institution of Engineering and Technology; 2006.
[Crossref] [Google Scholar]
[8]
Miguel JM, Lopez-martin AJ, Acosta L, Ramirez-angulo J, Carvajal RG. Using floating gate and quasi-floating gate techniques for rail-to-rail tunable CMOS trans conductor design. IEEE Transactions on Circuits and Systems I: Regular Papers. 2011; 58(7):1604-14.
[Crossref] [Google Scholar]
[9]
Srivastava A, Srinivasan C. ALU design using reconfigurable CMOS logic. In the 45th midwest symposium on circuits and systems 2002. IEEE.
[Crossref] [Google Scholar]
[10]
Kahng D, Sze SM. A floating gate and its application to memory devices. The Bell System Technical Journal. 1967; 46(6):1288-95.
[Crossref] [Google Scholar]
[11]
Holler, Tam, Castro, Benson. An electrically trainable artificial neural network (ETANN) with 10240'floating gate ‘synapses. In international joint conference on neural networks 1989 (pp. 191-6). IEEE.
[Crossref] [Google Scholar]
[12]
Gupta R, Gupta R, Sharma S. Design of high speed and low power 4-bit comparator using FGMOS. AEU-International Journal of Electronics and Communications. 2017; 76:125-31.
[Crossref] [Google Scholar]
[13]
Maryan MM, Azhari SJ, Ghanaatian A. Low power FGMOS-based four-quadrant current multiplier circuits. Analog Integrated Circuits and Signal Processing. 2018; 95:115-25.
[Crossref] [Google Scholar]
[14]
Aggarwal B, Dhawan R, Narang N. A new design for compact floating-gate transistor based low-voltage four-quadrant analog current multiplier. Arabian Journal for Science and Engineering. 2022; 47(11):14455-70.
[Crossref] [Google Scholar]
[15]
Dhawan R, Aggarwal B, Narang N, Rai SK. A new low voltage current mode analog multiplier/divider circuit based on FGMOS translinear loop. Iranian Journal of Science and Technology, Transactions of Electrical Engineering. 2022; 46(2):381-94.
[Crossref] [Google Scholar]
[16]
Bansal U, Gupta P, Tayal R. A high gain and high bandwidth three stage amplifier using FGMOS and 0.5 V dual supply. Analog Integrated Circuits and Signal Processing. 2020; 103(2):247-58.
[Crossref] [Google Scholar]
[17]
Domala N, Sasikala G, Raj N. Low voltage high bandwidth FVF current mirror using quasi floating self-cascode output stage. Analog Integrated Circuits and Signal Processing. 2024; 119(1):15-27.
[Crossref] [Google Scholar]
[18]
Chhabra A, Aggarwal B, Senani R. Low voltage squarer/divider circuit based on FGMOS. In 11th international conference on internet of everything, microwave engineering, communication and networks (IEMECON) 2023 (pp. 1-6). IEEE.
[Crossref] [Google Scholar]
[19]
Mehta UC, Mehta N, Bansal U. FGMOS based low power analog subtractor. In international conference on computing, sciences and communications (ICCSC) 2024 (pp. 1-5). IEEE.
[Crossref] [Google Scholar]
[20]
Keleş S, Keleş F. Low voltage-low power wide range FGMOS fully differential difference current conveyor and application examples. International Journal of Electronics. 2024; 111(3):499-514.
[Crossref] [Google Scholar]
[21]
Kandpal J, Tomar A, Agarwal M. Design and implementation of 20-T hybrid full adder for high-performance arithmetic applications. Microelectronics Journal. 2021; 115:105205.
[Crossref] [Google Scholar]
[22]
Gupta R, Gupta R, Sharma S. A high-speed, low-power, and area-efficient FGMOS-based full adder. IETE journal of Research. 2022; 68(3):2305-11.
[Crossref] [Google Scholar]
[23]
Gladwin SJ, Mangayarkkarasi M. Design and performance comparison of 4-bit adders using different logic styles. Journal of Computational and Theoretical Nanoscience. 2018; 15(3):949-60.
[Crossref] [Google Scholar]
[24]
Ramkumar E, Gracin D, Rajkamal P, Bhuvana BP, Bhaaskaran VK. Design and analysis of low power and high speed FinFET based hybrid full adder/subtractor circuit (FHAS). In international symposium on smart electronic systems (iSES)(Formerly iNiS) 2020 (pp. 281-4). IEEE.
[Crossref] [Google Scholar]
[25]
Goel S, Kumar A, Bayoumi MA. Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2006; 14(12):1309-21.
[Crossref] [Google Scholar]
[26]
Sharma U, Jhamb M. Efficient design of FGMOS-based low-power low-voltage XOR gate. Circuits, Systems, and Signal Processing. 2023; 42(5):2852-71.
[Crossref] [Google Scholar]