Abstract

The emergence of power-constrained applications demands high-speed and energy-efficient circuit designs. A multiplexer (MUX) is a fundamental building block in datapath design, bus systems, and memory access, enabling data selection, signal routing, and arithmetic operations in very-large-scale integration (VLSI) systems where signal selection is required. This research paper proposes two 2:1 MUX designs based on pass transistor logic (PTL). The proposed designs aim to minimize switching activity, parasitic capacitances, and leakage currents, thereby enhancing overall performance and power efficiency. A comparative analysis with existing complementary metal–oxide–semiconductor (CMOS)-based designs is performed using Hewlett-Packard Simulation Program with Integrated Circuit Emphasis (HSPICE). The simulation results demonstrate improvements in delay, power consumption, and energy efficiency across various supply voltages (VDD) through the evaluation of key performance metrics for the proposed designs.

Keywords

Pass transistor logic (PTL), Multiplexer (MUX), Very-large-scale integration (VLSI), Low power design, Energy efficiency, HSPICE simulation.

Cite this article

Dua T, Singh N, Kumawat R. Low power and high speed 2:1 multiplexer designs using pass transistor logic. International Journal of Advanced Technology and Engineering Exploration. 2026;13(135):303-318. DOI : 10.19101/IJATEE.2024.111101724

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