When working for low power application the main estimation is to reduce leakage components and parameters. This stanza explores a vast link towards low leakage power SRAM cells using new technology and devices. The RAM contains bi-stable cross coupled latch which has V_th higher in write mode access MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and lower V_th in read access mode MOSFET which is preferred for low leakage current and power without any distortion. The most promising substitute which are replacing bulk CMOS is DELTA (fully Depleted Lean channel Transistor) or FinFET (Fin-shaped field-effect transistor). For better performance and lower leakage parameters we can use FinFET either be shorted gates or independent gates. DELTA gates has good Short Channel Effects (SCE’s) compared to conventional based CMOS. Static Random Access Memory (SRAM) plays a most significant role in the microprocessor world, but as the technology is scaled down in nanometers, leakage current, leakage power and delay are the most common problems for SRAM cell which is basically designed in low power application. About 40-50% of the total power of the SRAM cell is dissipated due to the leakage occurs from the transistor. In this paper we compare the performance parameters of conventional 6T SRAM cell with FinFET based 6T SRAM cell. And determines that during write operation of FinFET based 6T SRAM cell gives leakage current is 69pA, leakage power is 7.581nW and delay is 20.55ns and for read operation of leakage current is 53.90pA, leakage power is 1.709µW and delay is 21.44ns.